About a half of year ago Intel has announced that they will mandate the 512-bit vector width and the full AVX-512 a.k.a. AVX10 support in all future CPUs, starting with Nova Lake. This includes all E-cores that will succeed the current Skymont/Darkmont cores, which have been the roadblock to general AVX-512 adoption.
Obviously, they were forced to do this to align with AMD. Moreover, Intel has announced that they will coordinate the future ISA extensions with AMD and with the major customers, so that all future Intel and AMD CPUs will remain mostly ISA compatible, at least for the user applications.
Not long ago, there has been published a joint AMD-Intel whitepaper about the future "AI Compute Extensions for x86", which will be present in future AMD and Intel CPUs for accelerating AI inference, extending the AVX-512 ISA, and which are similar to the Advanced Matrix Extensions currently supported by some of the Intel server CPUs, but the new ISA extensions are better compatible with AVX-512.
This document demonstrates that at least for now Intel and AMD have understood that implementing a compatible ISA is their greatest moat against Arm and other competitors, so they should better coordinate their extensions instead of trying to pull in different directions.
For example, Intel stated this:
> Intel® Advanced Vector Extensions 10 (Intel® AVX10) introduces a modern vector Instruction Set Architecture (ISA) that will be supported across future Intel® processors.
They don't actually say “all”, and it is probably meant to apply to future microarchitectures anyway. Depending on various factors, Intel may end up designing new CPUs based on existing microarchitectures well into the 2030s.
Page 18:
> 3.1 INTEL® AVX10 INTRODUCTION
> ...
> This ISA will be supported on all future processors, including Performance cores (P-cores) and Efficient cores (E-cores).
As you see, now they actually say "all future".
The Intel Nova Lake desktop and laptop CPUs and the Diamond Rapids server CPUs will mark a jump in the Intel ISA, by changing the CPUID CPU family number for the first time after a few decades and by introducing not only AVX-512 across all cores, to match AMD, but also the APX ISA extension, which adds features that remove some of the advantages of Arm Aarch64, by increasing to 32 the number of general-purpose registers and by adding double-register load/store instructions.
I'm excited about Nova Lake as well. Maybe not so much for the EGPRs (maybe we should have made 4 of the new registers callee-saved?), but there are other goodies as well.
Only in the now obsolete Intel server and workstation CPUs from the Skylake Server, Cascade Lake and Cooper Lake families, using AVX-512 was a win when a great number of vector instructions were executed, but it was a loss when only a small number of vector instructions were executed.
This was caused by a really stupid Intel voltage and frequency controller, which could not react quickly enough to changes in power consumption. Because of this, it dropped preemptively the clock frequency, before there was any need for this, for fear that the CPU will overheat if the power consumption will increase in the future and the voltage/frequency controller will not be able to decrease it fast enough, before reaching the temperature limit. For the same reason, the clock frequency was kept low a very long time after the last vector instruction seen.
Now this is pretty much history, because few have kept those 7 to 10 years old inefficient servers and those who have kept them normally run workloads that either use a lot of vector instructions or they do not use such instructions.
Nowadays the only reason for not using AVX-512 is when the software is intended to be widely used and one does not want to distribute 2 versions, one with AVX-512 for AMD or P-core Intel CPUs and one with AVX for E-core or hybrid Intel CPUs or very old AMD CPUs.