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by adgjlsfhk13 hours ago |
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upvoteby jacquesm3 hours ago|
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Bit manipulation instructions are part and parcel of any curriculum that teaches CPU architecture. They are the basic building blocks for many more complex instructions.

https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html

I can see quite a few items on that list that imnsho should have been included in the core and for the life of me I can't see the rationale behind leaving them out. Even the most basic 8 bit CPU had various shifts and rolls baked in.

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upvoteby rwmj3 hours ago|
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This is the reason behind the profiles like RVA23 which include bitmanip, vector and a large number of other extensions. Real chips coming very soon will all be RVA23.
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upvoteby jacquesm3 hours ago|
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Neat. I can't wait to get my hands on a devboard.
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upvoteby NekkoDroid2 hours ago|
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The earlierst I know of coming is the SpaceMit K3, which Sipeed will have dev boards for.
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upvoteby statusfailed1 hours ago|
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The Milk-V Jupiter 2 (coming out in April) is RV23 too
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upvoteby jacquesm1 hours ago|
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Nice board but very low on max RAM.
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upvoteby kevin_thibedeau2 hours ago|
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32-bit barrel shifters consume significant area and RISC-V was developed to support resource constrained low cost embedded hardware in a minimal ISA implementation.
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upvoteby pezezin28 minutes ago|
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The 32-bit ARM architecture included a barrel shifter as part of its basic design, as in every instruction had a shift field.

If a CPU built in 1985 with a grand total of 26 000 transistors could afford it, I am pretty sure that anything built in this century could afford it too.

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upvoteby snvzz11 minutes ago|
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26k is a lot of transistors for an embedded MCU.

You'd be excluding many small CPUs which exist within other chips running very specialized code.

As profiles mandate these instructions anyway, there's no good reason to complicate the most basic RISC-V possible.

RISC-V is the ISA for everything, from the smallest such CPUs to supercomputers.

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upvoteby adgjlsfhk12 hours ago|
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IIUC this is a lot less true in the modern era. Even with 24nm transistors (the cheapest transistor last time I checked), modern microcontrollers have a fairly big transistor budget for the core (since 80+% of the transistors are going to sram anyway).
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upvoteby jacquesm2 hours ago|
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You can save a lot of silicon by doing 8 or 16 bit shifters and then doing the rest at the code generation level. Not having any seems really anemic to me.
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upvoteby hackyhacky3 hours ago|
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> One of the best parts about RiscV is that you can teach a freshman level architecture class or a senior level chip building project with an ISA that is actually used.

Same could be said of MIPS.

My understanding is the RISC-V raison d'etre is rather avoidance of patented/copywritten designs.

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upvoteby adgjlsfhk13 hours ago|
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the avoidance of patent/copyright is critical for (legally) having students design their own chips. MIPS was pretty good (and widely used) for teaching assembly, but pretty bad for teaching a class where students design chips
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