Take Epyc processors. On certain ones, after certain RAM amount, populating all the slots causes the cpu to kick the RAM speed to a lower tier.
You’re then limited to capacities of two sticks.
Weird, but it has to do with power requirements. Abutting above the threshold had to be buffered, which increases latency.
Have recent boards/cpus fixed the instability problems people had with 4 sticks of DDR5 yet?
I was shocked when I saw folk saying you can't use 4 slots. It would mean that a one stick build would have an upgrade path but if you started with 2, you'd have to replace them.
In 2026 the bottleneck is wafer size as fabs are booked out making things for AI.
Or is it just binning by defects, the lower sized parts are just the full size but with defects disabling large chunks of the silicon as I would expect?