Hard to tell the exact ancestry of Lakemont. It might be a from-scratch scalar design that just so happened to target the i586 instruction set, but with a 486 style 5-stage scalar pipeline. Or it might be forked and hacked down from something more modern, like Atom.
It's a very configurable core. There are versions with just the FPU and NX bit turned off. MCU variant goes further, turning off segmentation, the BCD/string instructions, xchg and the AF/PF flags.
Intel did a talk on the MCU core at hot chips [1], which gives you a better idea of how they made/configured it (but doesn't give much insight into where the original Lakemont core came from).
But modern hardware design acts kind of like software these days. They write verilog code, they fork designs off, they share code or entire modules between teams. The code is often configurable. And then they throw the code + configuration at automated tooling which spits out reasonably good gate layouts.
CPUs today are so powerful and complex that it takes highly capitalized companies many years and generations to get something that approaches modern performance expectations. Arguably we’re still waiting for a RISC-V CPU to reach the market that has decent performance.