Since we're in feedback mode, 2.16 has no BitLineBar reference to feed to the comparators. I had to cheese the level by connecting the "capacitor" outputs straight to the outputs, and it worked.

On the capacitor though, the capacitor level is weird as you don't build the capacitor charge system with transistors. Though I definitely get that the simulation engine is for digital stuff, not analog :)

Also a general feedback on the time-based challenges: dial them back. A lot. Most of them are just not interesting and have zero learning value. In fact, the "DRAM refresh" one just made me quit the game (clicking on 8 rows to keep them fresh). Okay, 10s is enough, I got the point. No need to hold up for a whole minute. Kinda same for the hex one. However, some of them are good, and the UI for the binary ones is great, especially for the two's complement one!

Small nitpick on the UI: some blocks don't have their connections aligned with the grid, making the wiring OCD-incompatible. But that's minor. It's a shame since the wire routing algorithm works quite well overall, and I'm impressed an LLM could produce that good of an UI!

Otherwise, quite a fun little game, if slow paced when one already knows some bits of digital logic. Keep up!

I'm still confused about 2.7 because it says that we have to use WL so that "the bit line (BL) connects to the storage element for reading or writing". But the accepted solution connects to the storage element only for writing, not for reading (the capacitor is always connected to the output for reading).

I would think that if you wanted to make it so that the storage element was connected either for reading or for writing by the WL and otherwise disconnected, you would need two transistors, not just one.

Perhaps this was meant to say "for writing either a 0 or a 1"?