This project seems to have a serdes block which seems to wrap whatever is in the PDK. Didn't look too far down but from a cursory glance it looked like it was built for an internal clock of 50 MHz (clock default to 20 ns) with an oversampling of 8: 400 MHz
replyIf those numbers are at all right it puts it in useful territory. Very much so for a first spin
For a first spin it looks overall pretty useful. The only nitpick I have would be that `operation` on the DSP tile should be from fabric instead of config (hardcoded in bitstream) otherwise I don't see a convenient way of resetting the accumulator(?)
Thanks for the suggestion on the DSP. Maybe I'll add new DSP tiles that are reconfigurable and keep the config based DSP tiles. I designed Aegis's Terra 1 to be a "good enough first gen" so that's why things are the way they are. I didn't want to over commit on the design for a first generation.
replyYeah, I did see there's been attempts but none really satisfied what I wanted out of it. I do know of FABulous and it seems good but not quite what I wanted. You can see that aside from yosys and nextpnr, it is quite self contained and even provides a very easy way of defining new silicon with Nix.
replyI know that IO is really the 2nd thing which sells FPGA's. I did design a basic serdes hardware that should just work for this first generation. I do want to do DDR IO cells in the future.
You can come work with us/for us and scale your SerDes design for us. That gets you actual wafer mask sets taped-out, a million chips and a WSI, not just test chips. A succesful SerDes will get you a job (at least in Europe).
replyHow fast will the SerDes run, 50 Mhz? It is not clear to me from the serdes_tile.dart source code. Can you share the verilog files?
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