Using video interfaces to transfer arbitrary data at high speeds is becoming a common trick for cheap boards with limited interfaces. Video inputs and outputs are generally highly mature and optimized to avoid dropping frames because everyone wants reliable video. Putting arbitrary data into video IO pipelines is a cheap way to get high speed IO through standard interfaces.
There is a cool project that uses cheap HDMI to USB capture devices for high speed data transfer out of cheap FPGA boards that have HDMI output [ https://github.com/steve-m/hsdaoh ]
In a perfect world, using PCIe directly would be a much better solution for a project like this. Having access to PCIe DMA support directly without relying on video IO peripherals is helpful for high speed ADC/DAC applications like this. It would also make the board more portable to other SBCs.
The ECP5-5G can do PCIe 2.0 x2 or PCIe 1.0 x4 which would provide around 8Gbps of data transfer. The problem is that the Raspberry Pi 5 only exposes a single PCIe lane to the user. The other 4 PCIe lanes of the Raspberry Pi 5 SoC are routed to the RP1 chip, which has the MIPI and CSI interfaces that are used in this project. So the data is going through a convoluted path instead of being connected to PCIe directly.
I would have to look at the details more closely, but even using the PCIe 2.0 x1 port (around 4 Gbps after overhead) on the Raspberry Pi would be close in bandwidth to the 5.6 Gbps number they give for their custom MIPI solution.
I think the Raspberry Pi 5 is a good first choice for most projects because it is widely support and has the largest community, but for a project like this the benefits of moving to a different SBC with PCIe 2.0 x2 would have been helpful. Keeping the project semi-independent of the SBC has a lot of benefits.
There is a line in the book Accelerando about how evolution did this with biological vision.
It's basically the highest bandwidth sense we have and evolved AFTER smell (chemical based) and auditory (gas pressure based) senses.
If you use PCIe, theoretically you don't need to reverse engineer how they implemented because you're not at the edge of the spec like they are here.
That said, I've thought about doing what they're doing countless times and it is nice to see it would work.
In the multi-tile array it apparently still only needs one Pi [1] as the FPGAs do the heavy lifting.
It says 1W TX power per antenna. So the 240 antenna array which draws 1500W has a transmit power of 240W.
I am sort of skeptical of the claimed gain... even at 6GHz, you need a 2-meter parabolic reflector to get 40dB, the array is 1/10th that diameter. EDIT: Ignore this second paragraph I misread the spec page.
And yeah, the agentic stuff is dumb, I've played a ton with doing low level SDR work on Opus 4.6 and it's truly ass.
Also, the "can't radar, plz don't ITAR" is horseshit. Some basic fw tweaks and you could get this to be, at the very least, a sweet FMCW setup.
My assumption is that they're trying to avoid crossing a legal line, as opposed to being personally invested in the idea of preventing radar use by a determined hobbyist.