Yep. The XOR trick - relying on special use of opcode rather than special register - is probably related to limited number of (general purpose) registers in typical '70 era CPU design (8080, 6502, Z80, 8086).
replyIndeed!!
replyMIPS - $zero
RISC-V - x0
SPARC - %g0
ARM64 - XZR
indeed. riscv for instance. also, afaik, xor’ing is faster. i would assume that someone like mr. raymond would know…
replyWhich part of "mathematical operations don’t reset the NaT bit" did you not understand?
reply> afaik, xor’ing is faster
replyEven tiny tiny CPUs can do sub in one cycle, so I doubt that. On super-scalar CPUs xor and sub are normally issued to the same execution units so it wouldn't make a difference there either.
On superscalars running xor trick as is would be significantly slower because it implies a data dependency where there isn't one. But all OOO x86's optimize it away internally.
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