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The iteration cycles are limited necessarily by the time between tapeout and getting chips off the line to a testable state. Maybe there's a little room to get an in-wafer test probe system built at the fab if each die has a standard pad layout, which would speed up the 'testable state' part of that timeline. But if your timeline is weeks (if only!) to months, there's little utility in being able to make incremental changes on a daily basis.

Plus, the only way fab costs become achievable are MPW runs which don't have adequate demand for multiple daily runs. The ones I've used run a few processes each month, rotating between most of them on a bimonthly to quarterly basis. They just don't fill up fast enough. But I'm small time fabless so maybe I'm missing something.

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Because you are dealing with the physical world where those different designs have different requirements that can conflict. It’s like saying all software is basically the same, why don’t you just abstract it all and run it on these Raspberry Pi’s.

You can do that, but it’s going to turn out poorly.

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The wafer manufacturing process takes weeks to months after a tape out.
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Accelerating this process sounds like a good focus for an SBIR (small business innovation research) RFP.
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A fab is not a small business!

Part of the delay is really just commercial. Fabs are optimized for utilization - throughput, not latency. A fab operator will prefer to queue up a load of work with as few gaps as possible, and your shuttle service run has to fit in one of the gaps. If you're NVIDIA and you've already booked the fab, there might not be so much delay. But not zero.

Nice little backgrounder: https://siliconmasters.co/blogs/our-blog/how-photomasks-for-...

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Just to buttress and embroider around your point that a fab is not a small business:

If there was a realistic way even to go from bare wafers to non-trivial custom chips in a small-batch fashion, you can bet there would be a cottage industry around it. I would love to live in a world where I could manufacture custom silicon as easily as I can manufacture a custom PCB or custom mechanical part.

But as it stands, quick-turn, rapid-proto "micro" fabs are obscenely expensive, to the extent that if you aren't absolutely certain you need the performance gains from custom silicon, justified by years of R&D that confirms the inadequacy of a multi-chip solution, then the idea is killed before any layout engineer is contacted.

Microfabs are either operated by research institutes, or they're booked solid for years, and basically printing money.

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The closest thing to that cottage industry is IMEC.
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> Fabs are optimized for utilization - throughput, not latency

I remember hearing some company trying for the speed

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> A fab is not a small business!

An SBIR is just a cost effective way for the government to put a number of PhDs/engineers to work on a problem.

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The time from tapeout to first samples is 3-4 months even for the biggest customers of TSMC.

Shorter for a metal only change.

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Accelerating the process is an incredibly obvious desire for literally everyone in the industry and there are already gobs of money being put into R&D.

The fact of the matter is that we're dealing with physical and chemical processes. It simply takes time for atoms to move across space. In many steps of the semiconductor fab process we are literally building up the chip by single-atom thick layers.

There's very finite limits to how fast you can throw atoms at a substrate. There are finite limits to how much time a photoresist must be exposed. There are finite limits to how fast chemicals can etch the surface. You can only saw a wafer so fast, you can only physically transport dice through space so fast.

These are problems that the entire industry wants to solve. These are problems at the bleeding edge of physics. This is not something a startup is going to solve, purely because you need to already have an entire semiconductor fab to iterate in.

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I sort of expected this to happen with tightly coupled customer-customizable chiplets inside a single package, instead. But it seems that packaging is also better left to Intel and AMD, I guess.
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> Multiple prototype designs could be grouped together

They do this, it's called a multi-project wafer (it's on Wikipedia). It doesn't help with lead time of course. As far as I know tape-out cost is a lot cheaper (if your design is microcontroller-scale) but still in the $100k+ region.

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