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The alt text of the first image describes it as the "Jalapeño inference chip".

As a non-RTFA-er. I'm assuming it's a wafer-scale chip, similar to the ones made by Cerebras.

EDIT: From TechRadar[0]: "The 300mm wafer that both CEOs are holding will generate about 50 to 60 ASICs."

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That made me chuckle but I guess if you have never seen one I could see how that assumption could be made.

If this photo is real I wonder what can be revealed about the approach they have taken by analyzing the architecture of what we can see.

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> That made me chuckle but I guess if you have never seen one I could see how that assumption could be made

It's more like that "wafer as a big-chip" (more formally, "WSE - Wafer Scale Engine") is now a reality (see Cerebras).

But in this case, the wafer will be split into a few dozen chunks.

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For reticle-limit chips, it's on the order of 100. And less than that once you filter out bad dies.

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Everybody here knows that.

What some don't know (including you) is that the industry is doing wafer-sized chips nowadays, of which Cerebras is the flagship company.

That's why the stock movement could be related, and that is why GP wrote that comment.