If you care about only capacity and cost yes, but not if you care about performance.
replyCan you back that up with anything about semi-recent nodes? The voltages are so fragile that I'm not convinced you would actually save space once you adjust the design to handle more levels.
replyIf it were possible, it would have been done already. The issue is the capacitors are already tiny, and barely can prevent a single bit decaying before refresh.
replydo you have a reference to exact / realistic scaling laws for the leakage currents as function of capacitor/dielectric dimensions and access transistor dimensions?
replyusing 4 (or 2^N) voltage levels stores 2 (or N) bits, so we can afford to make the structures larger
why would this approach make sense for NAND flash but not DRAM?
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