> We’ve accepted lack of ECC because Intel decided it would be a product line differentiator, and serious customers who didn’t want random crashes or to lose data would buy chips with ECC.

AMD has been allowing ECC on lots of regular hardware for a long time.

People don't tend to buy ECC for desktop use because it costs significantly more (used server ram is/was often cheap... but it often doesn't work in desktop boards), and the performance specs are poor.

My home servers are mostly retired desktops, so they get my old desktop ram and I don't want to pay premium prices for jedec speed ecc ram on my desktops, thanks.

Since DDR5 doesn't include reporting on bit errors (afaik), it likely means much fewer single bit errors, but most experienced errors will be multi-bit. Although, I dunno what proportion of bit errors is on the ram chips and what's on the bus... there's no protection from bus errors.

If there were reporting, you could replace chips with high error rates, but without reporting you'll keep running them until they fail enough to notice.

DDR5 on-die ECC is to achieve acceptable yields in the face of denser process nodes that decrease the reliability of RAM cells. It’s not clear how much of an improvement that is to what we had before, other than allowing for higher RAM speeds. It doesn’t replace side-band ECC.

I know that LPDDR5 has ECC, and not just single bit AFAIK, but if you enable it you lose some memory capacity (the 128 bit bus minus 16 bit for ECC error correction, making it effectively 112 bits)