Is it built in different silicon, is it physical steps that's incompatible (ie its actually incompatible), is it different physical preparations that needs to be made (making it economically infeasible to combine)
I cannot help but wonder, even if the answer doesn't change anything in my life.
At a very abstract level, when you're manufacturing DRAM you need to manufacture a lot of circuit elements that have HIGH capacitance, since a DRAM cell is basically a capacitor and the higher its capacitance the less frequently it needs to be refreshed.
On the other hand, when manufacturing logic (CPU/GPU/ASIC) you want to minimize the capacitance of almost all circuit elements, since capacitance introduces delay and switching energy cost.
Nearly everything about the manufacturing processes for DRAM and logic is optimized around this fundamentally incompatible figure of merit.
I worked on the development of Intel's eDRAM process, which was used to integrate DRAM into the CPU/GPU die for Iris Pro embedded graphics from 2013-23. https://ieeexplore.ieee.org/document/6576667/
A Reddit user explains a bit here.
This in turn affects the electrical properties: parasitic resistance/capacitance, gate dielectric properties and so on. The dielectric in particular is critically different between DRAM and regular CMOS, because DRAM needs to minimise leakage (as that determines how long the memory lasts between refresh cycles).
Regular factories will retool somewhat between jobs. Because it is quite difficult to finetune a silicon process node, it is more common that a fab will set up for a particular node and then switch to "do not touch or change anything under any circumstances", as doing so may wreck yields.
("different substrate entirely" does exist: that's GaN, for power transistors in phone chargers, and SiC, for even higher power transistors.)
What's more, the configuration and flow of the machines used for each step are quite sensitive: you cannot in general just stand up another fab with the same machines, apply the same settings, and hit go on a new chip design and expect any yield: you need to dial in each step, certainly for each process, and likely for each design. This makes switching things around more difficult as well.
So, while in general a fab will have certain common features: spin coaters, photolithography machines, vapor deposition chambers, ovens, etc, the number and specification of each one will vary based on the process, and a production fab will generally not want to change their process drastically, or even to swap between different designs too often.
If you want to know more, the Asianometry youtube channel has some fairly good deep dives, such as [2] going through a decent bunch of the 45nm production process, or [3] doing the same for (early) DRAM.
[0]: https://www.youtube.com/watch?v=Bln-v9LmZ3E
[1]: https://i1.wp.com/semiengineering.com/wp-content/uploads/201...
You can't find an explanation why they're different for the same reason you can't find an explanation why writing poetry and riding a unicycle isn't the same process.
and cost per transistor stopped decreasing at ~20-30nm, now small nodes are targetting energy efficiency (and thus performance, since heat is the main limiter)
Granted the machines that make them become more expensive, but that's capital expenditure, which gets amortized as time goes on.
So there are two forces here working against each other.
Supply and demand coupled with the fact that a RAM fab can't (trivially) output compute chips, and vice versa, a compute fab can't output RAM. It's two completely different supply chains.
Also you calculate in the machine cost and R&D.
RAM hiked because the demand spiked and these companies are now in power. Before apple and other companies told them the prices and had hardly any money for investment.