Indeed, this is a problem for an energetic student who has free access to every tool in the Cadence, Synopsys, and Mentor portfolios: take the GDS-II layout, run it through extraction, generate a netlist, convert to higher-level blocks ("netlist-to-gate recovery"), translate to RTL HDL, then attempt to work out "what it does."

This is just a job posting in disguise for Jane Street: solve the puzzle, get a call from one of their recruiters.

It's even easier in this case because they've included the original verilog source ....