Pcie dma uses BAR registers setup by cpu. It will contain information about the physical memory address for one. On newer systems, there is NVLINK C2C which is more tightly integrated and less general.

Regardless, my point was the the article is about vram.

However, there is one situation when vram access itself uses the bar, to be fair. When you do P2P dma, code (kernel, either the inbuilt version or the one in the nvidia driver) running on the cpu sets up the DMA engines's GART to contain the BAR1s of the other.