GREAT classic question (with a well-defined answer)

In general, the reason why modern CPUs are so complex is because the gap in performance between CPU and memory has grown massively over time.

In the old days, something like a 6502 was running nearly synchronously with RAM.

That gap has grown massively over time; a modern CPU is orders of magnitude faster than RAM. So they have to jump through a lot of loops to avoid simply idling 99.99% of the time while they wait for some new data or instructions from RAM. On-CPU cache memory is one answer. Branch prediction and speculative execution are others. As you may imagine, speculatively executing code based on branch prediction is very complex because you must roll back any side effects from that execution if your prediction turns out wrong.

Example:

   # assume `i` is a value stored in main memory
   if i == 42
      j += 1
      k -= 1 
      l = 666
   else
      z = 123
      q = 5879873

Waiting for `i` to arrive from main memory might take thousands of CPU cycles. So instead we will execute one, and possibly both of those branches. But we'll need to undo those side effects if turns out we executed something with an invalid prediction. It's complex, and messy, but still better than sitting around doing nothing for thousands of cycles.

That's why we can't just take an R2000 and scale it up to 3ghz. I mean, we could, but it wouldn't work very well unless we also had low-latency 3ghz main memory to pair with it.

> wonders how ARM did that

Acorn co-founder Hermann Hauser famously joked that he gave the original ARM microchip design team two distinct advantages: no time and no resources. With no money for a large crew or complex hardware, the tiny core team had to keep the processor design exceptionally simple, which ultimately birthed the revolutionary RISC architecture.

It also had to run in simulation on a BBC micro… Probably with a second processor via the Tube interface, but still.

A fairly deep dive into it

https://www.righto.com/2015/12/reverse-engineering-arm1-ance...

ARM1 has no cache memory, no hardware multiply and division, no MMU and no cache.