I’m going to give you the benefit of the doubt: in your mothertongue, the meaning of “design” is not as broad as in English?
>The biggest cores on the the Xring O3 are the C1-Ultra. C1-Ultra really powerful cores. They support SME2 (Scalable Matrix Extension 2) for matrix/AI acceleration, SVE2 for data parallelism (SIMD).
Xiaomi has made the XRING 03 boast a larger die size than the XRING 01,
measuring 133mm² compared to its predecessor’s 109mm² dimensions This change
was deemed necessary as the flagship SoC features 16MB of SLC cache, not to
mention a new “6 + 4” CPU cluster that comprises two ARM C1-Ultra cores
running at 4.35GHz, four C1-Premium cores operating at 3.68GHz and lastly,
four C1-Pro cores running at 3.15GHz. [1]
0. https://www.arm.com/products/silicon-ip-cpu/c1-ultra1. https://wccftech.com/xiaomi-xring-03-official-tsmc-3nm-n3p-l...
A revision or other reply would benefit from explaining how their value chain x location correspondence is wrong - perhaps missing a step?
Though, in anticipation of a revision, I wonder if its simple as you thought the cores were custom-designed by Xiaomi instead of standard ARM.