This isn't software. The time, labor, and equipment costs of the first wafer dwarf the redesign cost, so it makes sense to get it right the first time. What if every build, compile, and link cost you $10M and 1 month? How would that change your work flow?
Most of the "AI" design tools today are focused on verification, validation and layout, which makes a lot of sense. They might help with architecture in the future (or making something high yield AND easy to fix in metal)?
You could run a small design on an MPW shuttle to reduce these costs, but your TTM get's longer, the yields won't be as high, and if you go to mass production you still face the huge mask costs.
Another place this might make some sense is reworking old large die 130nm designs on 8" wafers to be newer 28mm designs on 12", there are a LOT of those. The mask costs are lower, the design is well understood with lots of process margin, and wafer/yield costs could be modeled and favorable. Of course analog scaling is a whole separate kettle of fish.
If people have millions of new chip designs that need making, perhaps that will be motivation to invent a new way of making chips. It might not be better at manufacturing a billion of the same chip, but maybe it’s better at producing a billion different chips. Then every HFT could have their own chip and people could try out all kinds of new designs without committing a fortune.
As far as home printing stuff: the clean room requirements are INSANE: just the HF (hydrofluoric acid) is crazy bad stuff that you could NOT get certified for general consumer use, no way, no how. And even if you did, you'd be crazy to buy something that comes with HF as part of the process.. And that's just ONE bad, bad chemical used by TSMC all the time.
FPGAs are the "faster-than-software / can make a custom chip" compromise - companies like Intel used to (not sure if they still do) use a ton of FGPAs to simulate new chip designs. Precisely because manufacturing state-of-the-art chips is so hard.
There's a reason e-beam lithography is only used to make masks, and why it's one of the most expensive parts of the manufacture.
The problem isn't lithography, though, it's all of the adjacent processes (ion implantation and a dozen other things) that are fab/process-specific and require even more complicated/expensive equipment.
Shuttle runs give you a true-to-process tapeout and are dirt cheap, so only universities and the like bother with direct-write.
That's for the most advance tech (sub 10nm and such). There is a lot of fab for chips that do not require the latest and greatest. If LLMs make it easier / more accessible to design ASIC, I think those fabs will be the one who will benefit the most.