They state it's for HBM wafer inspection equipment:

OKI Group printed circuit board (PCB) company, has successfully developed 124-layer PCB technology for wafer inspection equipment designed for next-generation high bandwidth memory, such as HBM

Since the latest semiconductors process an enormous number of signals and the number of wafer-mounted chips increases due to process miniaturization, it is necessary to increase density and more layers on the PCBs used in inspection equipment.

In their linked semiconductor testing page[1], they mention conductive paste. So seems they test whole wafers by having the whole wafer put on such a PCB, using conductive paste instead of solder or similar, and the high layer count is then to be able to bring out all the connections (pins) from each chip to the testing circuits while maintaining the high signal integrity required for the high-speed signals.

HBM makes it worse since it is fast due to its very high bus width, 1024 bits wide, moving to 2048 bits wide[2]. So to test a HBM chip on a wafer before its cut and bonded to a GPU chip or such, you'd need to bring out those thousands of connections per chip on the wafer. Hence the need for so many layers compared to a regular PCB.

That's my semi-informed take.

[1]: https://www.oki-otc.jp/en/products/test.html

[2]: https://www.nextpcb.com/blog/hbm-vs-gddr7-pcb-layout#pcb-hbm

The number of levels of traces and gates laid out is an important aspect of how much sophistication and capability available to connect ICs on a pcb. You are laying out power and ground and communication. There are lots of other considerations like the complexity of what you can plan to layout using software. But you stack layers of traces to add capability. More layers is naively more capability.

This article from Aug 2026 says 20 layers are for complex designs. https://www.pcbasic.com/blog/pcb-layers.html. So 124 layers looks like a huge increase.

Not my area, probably got it all wrong, hope this is useful.

The PCB itself often forms several different components these days.

Higher density chip packing is only one advantage. Unlikely going to see such things in cost-optimized consumer products. =3