Intel is weird with their stuff like that, I wrote about how they introduced and then dropped an SHA instruction that could be used to optimize hashing (useful for things like block checksum hashes on storage servers) before: https://neosmart.net/blog/will-amds-ryzen-finally-bring-sha-...
The ECC in DDR5 is on-die ECC and that's not "real" ECC, it's what DDR5 needs to not fail. Side-band ECC is the standard method, employing extra memory chips and 72bit memory. OEMs mix these in the marketing materials to fool the users into thinking they buy the better option.