One of the reasons the M series of processors from Apple can manage such a high instruction throughput is that the instructions are fixed length, which allows them to just be slotted into the multiple instruction decoders. The instructions compression provided by CISC in the amd64 instruction set means that the instructions do not start at predictable places, which makes it much harder to decode many instructions per clock cycle.

> CISC instructions take up less space than the equivalent RISC instructions

In theory CISC instructions take less space than the equivalent RISC instructions, but x86 has lots of legacy features which makes it far less efficient than a CISC could be.