I don't think that's quite fair - this guy is clearly quite familiar with CPU design, it's very easy to run coremark, dhrystone, etc. to get a decent idea of performance, and for verification there's a reference model written in Sail you can compare against (though tbf it sounds like he didn't). AI is good at writing large test corpuses these days too.
replySo I would say it is relatively easy to tell if a vibe coded RISC-V CPU is actually good today. It's not like non-vibe coded RISC-V CPUs were amazingly well verified before anyway (except Ibex anyway). Even CVA6 has had some embarrassing bugs.
I expect this is a decent RISC-V core, but I also expect I could make one just as easily.
I don't think chip design comes down to knocking out a theoretically correct design. Then you fab it and it can't run at more than 37mhz LOL.
replyI think you don't know what you don't know here.
I wish you’d use your knowledge to add to the discussion rather than discourage others.
replyI do know about physical design too. Just because somebody doesn't explain every single thing in a comment doesn't mean you win the argument by highlighting something they didn't mention.
replyI'm sorry, I didn't mean this to be personally critical of you. I'm talking generally about saying to an AI "make a chip don't make any mistakes" and then thinking there is any chance of getting something that isn't trash in return, and being confident of that even though one doesn't have the domain knowledge to know if it's trash or not.
replySpecifically, for an advanced superscalar chip design, it is unlikely this guy single handedly, with claude or whatever, produced something highly valuable where hundreds of professional chip designers have failed.
you might even note that the author posted here that they closed timing at 500MHz on nangate45...
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