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Oh, I didn't notice this capacitor bug, I changed it to add an enable gate for 2.4 (for context, i created 2.4 after 2.7 b/c i thought 2.7 wasn't obvious enough for some ppl). 2.4 kind of needs the enable pin b/c of how my simulation system works. Yeah, I felt pretty conflicted on the capacitors whilst building, theres actually a note about this in the capacitor info block in later levels, but I couldn't really make a true capacitor compatible with the underlying simulation system I had built (I should have thought it through from the start).

Ill fix the truth tables bug (i think i know the issue), the stars come from playing in endless mode

I used claude quite a bit, it struggled through a lot of this (wiring and simulation systems in particular), but managed to crank this out, for the graphics i was extremely detailed in terms of what i wanted i'd say

by tuetuopay12 hours ago|

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Since we're in feedback mode, 2.16 has no BitLineBar reference to feed to the comparators. I had to cheese the level by connecting the "capacitor" outputs straight to the outputs, and it worked.

On the capacitor though, the capacitor level is weird as you don't build the capacitor charge system with transistors. Though I definitely get that the simulation engine is for digital stuff, not analog :)

Also a general feedback on the time-based challenges: dial them back. A lot. Most of them are just not interesting and have zero learning value. In fact, the "DRAM refresh" one just made me quit the game (clicking on 8 rows to keep them fresh). Okay, 10s is enough, I got the point. No need to hold up for a whole minute. Kinda same for the hex one. However, some of them are good, and the UI for the binary ones is great, especially for the two's complement one!

Small nitpick on the UI: some blocks don't have their connections aligned with the grid, making the wiring OCD-incompatible. But that's minor. It's a shame since the wire routing algorithm works quite well overall, and I'm impressed an LLM could produce that good of an UI!

Otherwise, quite a fun little game, if slow paced when one already knows some bits of digital logic. Keep up!

by Jaso102412 hours ago|

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lol, I encountered the same thing w/ the Dram one in particular during testing (I passed it by using number keys, but probably was a sign to remove)

Thanks, I appreciate all the feedback, fixes coming in the next push

by schoen6 hours ago|

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I'm still confused about 2.7 because it says that we have to use WL so that "the bit line (BL) connects to the storage element for reading or writing". But the accepted solution connects to the storage element only for writing, not for reading (the capacitor is always connected to the output for reading).

I would think that if you wanted to make it so that the storage element was connected either for reading or for writing by the WL and otherwise disconnected, you would need two transistors, not just one.

Perhaps this was meant to say "for writing either a 0 or a 1"?

by BoiledCabbage10 hours ago|

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Agreed, truth tables one is important. But it's backwards, you test people on truth tables before teaching them.

If someone is seeing this for the first time they may have never seen some of those gates and you quiz them.

Then finally after passing the quiz, you define NAND and NOR and Inverter.

Swap the teaching one to be the intro to the truth tables one.

Second bit of feedback is the timer. Increase the time allotted. I know them very well and still was struggling to get all the input correct before the timer hit. Or consider possibly just eliminating the timer completely - if your goal is to be sure that they know them.

by Jaso10249 hours ago|

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good point, made an update that added difficulty levels to the minigames (handles the timer), and i'll probably move the truth tables minigame to after the user builds the truth tables, thx