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by adrian_b15 hours ago |
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upvoteby indrora8 hours ago|
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> Designing a good 64-bit ISA [...] is easy [...] could design such an ISA in a couple of weeks

Let me know when you've got it all worked out and published. Should be easy, right?

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upvoteby exmadscientist4 hours ago|
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It is the easy part. Four weeks is plenty of time.

That's why it's so bizarre that the RISC-V design is so awful.

The hard part is the software support side (though, as comments elsewhere in the thread point out, AI is pretty helpful there) and then those lovely pieces like specifying the precise behavior of interrupts.

If it had a snowball's chance in hell of going in to any kind of production anywhere, I'd have no problem spending the next month laying out an ISA. But, again, as this thread makes very, very clear: ISA really just doesn't matter.

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upvoteby trollbridge15 hours ago|
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The effort to support architectures is now minimal with AI assistance. I made a hobby architecture (based on Intel, but with some changes; I was making an "alternate history" as if a few decisions in the past had been different) and it was pretty much trivial to spit out support not just in gcc and llvm, but I also, for fun, made WATCOM backends and a few other things.

With that said, RISC-V is a nice baseline for designing another architecture. Start with RISC-V, and go from there.

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upvoteby jcranmer12 hours ago|
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The main difficulty in support isn't actually making the changes (which is going to be largely defining various tables and other boilerplate, unless your ISA is really weird and does something unusual), it's in doing all of the politics necessary to get those changes committed upstream.
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upvoteby orbifold11 hours ago|
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Maintining this type of long time fork is the kind of mind numbing, tedious thing LLMs are actually exceptionally good at. I did some backend work on Lean4 compiler and then they switched out parts of the codegen, it took Codex less than an hour to recover the feature set I had implemented but on the new backend.
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upvoteby skydhash13 hours ago|
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> and it was pretty much trivial to spit out support not just in gcc and llvm, but I also, for fun, made WATCOM backends and a few other things

No links? You may have dreamt about it instead.

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upvoteby pseudohadamard7 hours ago|
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That's why I've never understood the point of RISC-V. Anyone can design a (reasonably OK) ISA. It's everything else that's the hard part. It's like announcing a new house, it's going to be pained Benjamin Moore Yellow Oxide and everything else is someone else's problem to sort out. Success! We've got a new house!

The only argument I've ever seen for RISC-V that's vaguely logical is that there's no licensing to Arm involved, but since I can get M0/M3 devices for a dollar or so with infinite tool and library support that's something that's totally irrelevant for most users. And if I don't mind going with Chinese suppliers there's no licensing to Arm being paid anyway.

Apart from being able to thumb your nose at Arm, I just can't see what the point of RISC-V is. Is that really all there is going for it?

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upvoteby jurgenburgen3 hours ago|
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> The only argument I've ever seen for RISC-V that's vaguely logical is that there's no licensing to Arm involved, but since I can get M0/M3 devices for a dollar or so with infinite tool and library support that's something that's totally irrelevant for most users.

How expensive is it to license the instruction set so you can expand it?

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upvoteby lmz2 hours ago|
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Surely those expanding the instruction set do not fall into "most users"?
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