One neat feature of 8087 instruction set is that it can be interspersed with x86 instructions in the code stream, giving you a simultaneous access to two processor chips working in parallel. This combo forms a real asymmetrical multi-processor system with certain opportunities for hardware-assisted code parallelization. If a thoughtful instruction scheduling is used, floating operations executed by 8087 work in parallel with the usual integer x86 code.
It schedules to these transparently for you, that's known as superscalar execution. To maximize occupation, out-of-order execution and simultaneous multithreading are used.
There were a few new instructions, too, mostly closing holes. You could left or right shift with a constant, while the 8086 had only 1 or the CX register. I think mul also gained a constant.
The fact that Intel released a CPU that could not be put in a PC probably indicates how low they estimated the survivability of the PC.
In the x86 microarchitectures superscalar came in Pentium and OoO got introduced in Pentium Pro.
(Superscalar is just having >1 pipelines, which at its introduction meant needing to manually schedule your code very carefully to take advantage of it absent the OoO execution. For example the frequently posted-about Doom optimizations and talk of the u and v pipes are about this. The scheduling didn't happen transparently in early superscalars, at best the cpu automatically stalled, and some archs (eg MIPS, i860, TI C3x) even visibly punted hardware detection of pipeline hazards and required the code to just not go there, see load delay slots and branch delay slots. )
Vs. Ken's Blog says "up to 100 times", and Wikipedia gives a lower estimate.
Theory: Your 100X experience compared Intel's "exact emulation" code (noted in the article) with native x87. That emulation would have to cover the myriad x87 oddities and corner cases which Ken describes. Vs. Ken's & Wikipedia's are comparing x87 to various "good enough" 8088 floating point libraries - so naturally much faster than Intel's exact code.
(And yes, speed might have been a low priority for the team writing Intel's emulator.)
But for a compiler to target, it's just so painful. It's so different from almost all other ways CPUs work. There's a reason both CPU and compilers prefer to avoid x87 when possible and use regular SIMD (SSE/AVX) instead.
Also, the arbitrary "Oh, and the registers are 80 bits wide" is also just one of those weird "Where did that number come from?".
The x87 ISA is essentially a one-address stack-based ISA (so unlike a pure stack ISA, you can reference another value on the stack without having to introduce something like a dup instruction). Which honestly isn't particularly painful to work with for a compiler; it's not usual, but there are other ISAs that are also stack-based (the JVM bytecode is the one that most immediately comes to mind).
The actual weirdness of x87, what makes all the compilers run away from it, is that the only values you can have on the stack are 80-bit extended-precision types. But people don't use those types in their code, they use 32-bit and 64-bit single and double precision, and compilers largely implemented these types by pretending that the x87 just used those value sizes in the first type (the only ones to actually get it correct that I'm aware of are Java's strictfp and Intel's icc, although the latter is merely just correctly implementing FLT_EVAL_METHOD==2). The end result is that compilers caused code to have essentially random and largely uncontrollable precision changes, which pissed a lot of users off, and the SSE units having regular scalar proper single and double precision types made it easier for compilers to switch to that rather than introducing the proper sequences to compile for x87.
With x87, however, that causes extra overhead from loads and stores that's best avoided. Unused stack space can be used to cache frequently used variables, but as operations must use ST(0) as one parameter, FXCH instructions must be used to swap around variables. Matching the x87 stack state on entry and exit of the loop is tricky and compilers historically have had trouble doing it. Different FPUs also differed on the efficiency of FXCH so there were often situations where a particular arrangement would double the speed of a routine on one CPU model and halve it on another.
The java compiler can practically pretend like the stack is infinite in size while a compiler dealing with x87 has to contend with spillage in all but the most trivial of algorithms.
One of the features that was advertised (mentioned in the iAPX 86, 88, 186 Microprocessors Part II book (July 1984)) was the ability to do exact arithmetic on integers up to 2^64, which is possible due to the 64-bit mantissa used in the 80-bit format.
I think the IBM 7030 Stretch CPU (from 1964) would be a likely contender for being one of the first 64-bit CPUs.
Otherwise most modern CPUs would be labeled as either 256-bit or 512-bit.
These days we generally label CPUs based on the width of the general purpose registers (though, it gets messy with things like the 68000). I personally suspect we won't ever see GPRs wider than 64 bits.
It's known that the 8087 was designed to attach to either the 8087 or Intel's 32-bit chip the 432. The contemporary rumor is it is in fact the floating point unit FROM the 432, a money-is-no-object project to make the "ultimate" 32-bit chips. The 432 itself had only stack-based registers, had all kinds of weird-length instructions, had to be split across multiple chips, and locked those registers away from programmers who were only allowed a slow high-level language to program it. Only when 432 was clearly failing was also paired to the 8086/88--a chip that itself was a crash project because of delays in the 432. Adding the very different 8087 to the 8088 was described as pairing a race car engine into a poky Volksagen bug.
Rumors mongered in 1982 by Hal Hardenburgh: http://www.easy68k.com/paulrsm/dg/dg06.htm, "Page 4" section.
On the other hand, getting floating point right in the 8087 was absolutely worth the effort. You can see the comparisons in a 1983 issue of Hal's newsletter on the Savage benchmark: http://www.easy68k.com/paulrsm/dg/dg26.htm. Go to "Timing Conclusions" and particularly "Error Conclusions" and beyond.
In other words there simply isn't room in the encoding to specify two operands, so they went for the stack model.
The issue is that x87 is 80bit floats which is awkward. As such, it still requires dedicated hardware.
Intel has proposed and abandoned pushing a new x86 architecture [1] which tweaks x86 instructions to fit better with the reality that everything is 64bit now. Part of that proposal was to make x87 work with 64bit floats instead of 80bit floats (which would have allowed it to share the same floating point units as the SIMD instructions).
[1] https://www.intel.com/content/www/us/en/developer/articles/t...
01b2086a 8975e4 mov dword ptr [ebp-1Ch],esi
01b2086d db45e4 fild dword ptr [ebp-1Ch]
01b20870 d95de4 fstp dword ptr [ebp-1Ch]
01b20873 d945e4 fld dword ptr [ebp-1Ch]
01b20876 d80dcc08b201 fmul dword ptr ds:[1B208CCh]
01b2087c d95804 fstp dword ptr [eax+4]
But clearly it has some support for using SSE2 when available, because it does use it for zeroing memory:
01b20884 0f57c0 xorps xmm0,xmm0
01b20887 660fd607 movq mmword ptr [edi],xmm0
01b2088b 660fd64708 movq mmword ptr [edi+8],xmm0To what degree did Intel assume their target market was either using hand-coded assembly, or written-for-x87 code with x87-specific compilers? Memory was not cheap in 1980, ditto 8087 chips, and oddities like the x86's 64K segments would discourage anyone trying to "just recompile" existing programs for x86/x87.
I'm curious to know - you say Intel's 8087 emulation code was a bit of a lump at 16KB, do you know if it emulated the 8087 microcode state machine or did it use a different strategy?